ATmega328

Scrap

  • 8-bit data width
  • 32 general purpose registers
  • 32KB program memory
  • 2KB SRAM
  • 1KB EEPROM
  • Stack kept in SRAM??
  • Lots of interrupts
  • Lots of addressing modes (direct, indirect, relative)

Register stuff:

  • Arithmetic and logical instructions operate directly on any registers, so less movement required.
  • LDI only loads values into R16-R31.
  • X (R27:R26), Y (R29:R28), Z (R31:R30) are used for indirect memory access (they contain 16-bit addresses). LD R16, X+ loads a byte from the address stored in X and auto-increments X.
  • CP R16, R17 performs a comparison and sets bits in the SREG status register, which we can then conditionally branch with.

Memory stuff:

  • Program and data memory have separate address spaces.
  • The program lives in flash, which has 16-bit words. Instructions are generally 16 bits wide. LPM is used to read a byte from flash (using byte addresses, not word addresses??).
  • SRAM contains working data and the hardware stack. The stack pointer (SPL and SPH) must be initialised to a value.

Instruction stuff:

  • LDI
    Load immediate constant
  • MOV
    Copy register
  • LDS
    Load from direct data address
  • LD
    Load from SRAM
  • ST
    Store to SRAM
  • STS
    Store to direct data address
  • PUSH
    Push register to stack
  • POP
    Pop register from stack
  • LPM
    Read program flash
  • ADD:
  • SUB:
  • ADC:
  • SBC:
  • INC:
  • DEC:
  • MUL
    Unsigned multiply
  • ADIW
    Add immediate to word
  • SUBI
    Subtract immediate
  • AND:
  • OR
    IOR
  • EOR
    XOR
  • COM
    NOT
  • NEG
    Two’s complement
  • LSL
    Logical shift left
  • LSR
    Logical shift right
  • ASR
    Arithmetic shift right
  • ROL
    Rotate left through carry
  • ROR
    Rotate right through carry
  • SWAP
    Swap nibbles
  • RJMP
    Relative jump
  • JMP
    Absolute jump
  • RCALL
    Relative call
  • CALL
    Absolute call
  • RET
    Return from call
  • RETI
    Return from interrupt
  • BREQ
    Branch if equal
  • BRNE
    Branch if not equal
  • BRCS
    Branch if carry set
  • BRCC
    Branch if carry clear
  • BRMI
    Branch if

Memory organisation

Instruction set

Status register (SREG):

Name
C Carry flag
Z Zero flag
N Negative flag
V Two’s compliment overflow flag
S Sign flag
H Half carry flag
T Transfer bit
I Global interrupt enable bit

Registers and operands:

Name
Rd Destination (and source) register
Rr Source register
R Result
K Constant data
k Constant address
b Bit position in register
s Bit position in status register
X,Y,Z Indirect address register
A IO memory address
q Displacement for direct addressing
UU Unsigned and unsigned operands
SS Signed and signed operands
SU Signed and unsigned operands

ADC

Add with carry. Adds registers Rd and Rr and the contents of the C flag and stores the result in register Rd. Sets H, S, V, N, Z, C.

0001 11rd dddd rrrr